The present invention relates generally to the packaging electronic components. More particularly, the present invention relates to the fabrication of a plurality of packaged electronic components on a single substrate.
Virtually every business in the world has become dependent, directly or indirectly, on electronic components such as integrated circuits. In addition, electronic components have permeated our personal lives through their use in systems that control or contribute to almost every aspect of our day from coffee making to network computing. This application of electronic components to what were once seemingly unrelated fields has created a huge demand for these components in increasingly diverse industries and locations. Consequently, there has been a corresponding increase in demand for better methods and structures to package electronic components. This demand has made electronic component packaging one of the most critical and competitive markets in the electronics industry.
To stay competitive, those of skill in the art of electronic component packaging are constantly seeking better ways to provide protection of the extremely fragile electronic components from environmental elements and contamination while, at the same time, providing a solution which does not significantly increase the cost of the finished, packaged electronic component to the system manufacturer or the consumer. In one effort to reduce the cost of individual packaged electronic components, those of skill in the art have developed prior art methods and structures that allow electronic component packaging companies to fabricate multiple packaged electronic components from a single substrate, i.e., multiple packaged electronic components are created at once using a single substrate.
FIG. 1A is an enlarged top plan view of a prior art multi-package array substrate 13. Prior art multi-package array substrate 13 is one of several types of prior art substrates such as the prior art substrate discussed in U.S. Pat. No. 5,981,314 entitled xe2x80x9cNear Chip Size Integrated Circuit Packagexe2x80x9d, issued Nov. 9, 1999 to Thomas Glen, Roy Hollaway and Anthony Panczak, and assigned to the assignee of the present invention, which is incorporated in its entirety herein. In FIG. 1A, a plurality of lines 56 oriented in the vertical direction, as well as a plurality of lines 58 oriented in the horizontal direction are illustrated. Lines 56 and 58 were included to define the sections 12 where each individual packaged electronic component is to be formed. (For clarity, in FIG. 1A only two sections 12 are labeled). As shown in FIG. 1A, the periphery of each section 12 is defined by lines 56, 58. However, in an alternative embodiment, instead of lines 56, 58, alignment marks and/or fiducials were provided for aligning prior art multi-package array substrate 13 in subsequent processing steps discussed below. Consequently, in some prior art embodiments lines 56 and 58 were not solid lines. In addition, even when lines 56 and 58 were solid lines, lines 56 and 58 were typically only marks on a first surface 18 of prior art multi-package array substrate 13.
As shown in FIG. 1A and FIG. 1B, a dam 59 is typically formed on a first surface 18 of prior art multi-package array substrate 13, around the perimeter of prior art multi-package array substrate 13. Dam 59 encloses sections 12, yet does not extend into any of the sections 12.
FIG. 1B is a cross-sectional view along the line IBxe2x80x94IB of FIG. 1A of prior art multi-package array substrate 13. In practice, prior art multi-package array substrate 13 would also include conductive through-holes and other features which are not illustrated in FIG. 1B for clarity. As shown in FIG. 1B, dam 59 extends from first surface 18 to a predetermined height indicated by dashed line 68 above first surface 18 thereby defining a pocket which can be filled with encapsulant as described in more detail below.
Referring back to FIG. 1A, each section 12 of prior art multi-package array substrate 13 typically has a plurality of metallizations 22 formed on first surface 18 of prior art multi-package array substrate 13. In addition, a plurality of contacts (not shown) formed on metallizations 22 and a plurality of conductive through-holes (not shown) formed through prior art multi-package array substrate 13 could also be included but are not shown in FIG. 1A and FIG. 1B for simplicity and to avoid detracting from the discussion at hand.
Metallizations 22 are typically formed using conventional techniques such as by forming a conductive layer on first surface 18 and then by masking and etching the conductive layer. Conductive through-holes (not shown in FIG. 1A and FIG. 1B) can also be formed using conventional techniques such as by drilling through-holes in prior art multi-package array substrate 13 and then plating the drilled through-holes with a conductive metal such as copper.
FIGS. 2A and 2B are cross-sectional and top plan views, respectively, of an exemplary section 12 of substrate 13 (FIG. 1A) further along in processing. As shown in FIG. 2A, a first surface 32 of an electronic component such as an integrated circuit (IC) chip 30 is typically mounted to first surface 18 of prior art multi-package array substrate 13 by a layer of adhesive 34. As shown in FIG. 2B, IC chip 30 is typically mounted to section 12 in a location central to metallizations 22. Also shown are bonding pads 38 located on a second surface 36 of IC chip 30. Bonding pads 38 are typically electrically connected to corresponding contacts 23 by bond wires 40, made of gold or aluminum for example, using conventional wire bonding techniques.
In an alternative prior art embodiment (not shown) instead of mounting first surface 32 of IC chip 30 to first surface 18 of prior art multi-package array substrate 13 and electrically connecting bonding pads 38 to contacts 23 and metallizations 22 using bond wires 40 as illustrated in FIGS. 2A and 2B, IC chip 30 is mounted to substrate 13 using a flip chip interconnection. In this prior art embodiment (not shown), second surface 36 of IC chip 30 is placed adjacent first surface 18 of substrate 13 and bonding pads 38 are electrically connected to contacts 23 and metallizations 22 directly, for example, by solder. An under fill material is then applied to fill the space between IC chip 30 and substrate 12 and also to encapsulate the flip chip interconnection between bonding pads 38 and metallizations 22.
FIG. 2C is a cross-sectional view of an exemplary section 12 further along in processing. As shown in FIG. 2C, a layer of encapsulant 42 is applied over the entire assembly. In particular, layer of encapsulant 42 covers IC chip 30 including bonding pads 38, bond wires 40, contacts 23, metallizations 22 and the remaining exposed first surface 18 of prior art multi-package substrate 13. Typically, layer of encapsulant 42 is formed of an electrically insulating encapsulant and can be laser marked for product identification using conventional laser marking techniques. Layer of encapsulant 42 is typically applied as a liquid and then dries, or is cured, to a hardened solid.
Referring back to FIGS. 1A and 1B, and in particular to FIG. 1B, layer of encapsulant 42 is applied by filling the pocket defined by dam 59 with encapsulant. Dam 59 prevents layer of encapsulant 42 from flowing off first surface 18 of prior art multi-package substrate 13. Typically, dam 59 has a height indicated by dashed line 68 above first surface 18 greater than or equal to the height of upper surface 48 of layer of encapsulant 42 (FIG. 2C) above first surface 18.
As also shown in FIG. 2C, interconnection balls 28, typically eutectic solder balls, are attached to contacts 27 using conventional techniques. FIG. 2D is a bottom plan view of the exemplary section 12 of prior art multi-package substrate 13 of FIG. 2C. As shown in FIG. 2D, interconnection balls 28 are typically arranged in an array thus forming a ball grid array. In alternative prior art embodiments, contacts 27 form interconnection pads for electrical interconnection with other components and interconnection balls 28 are not formed. In other prior art embodiments, the interconnection balls or pads can be arranged adjacent Ad the perimeter of section 12, i.e. can be arranged near lines 56 and/or lines 58, instead of being arranged in an array fashion as in FIG. 2D.
Once applied, layer of encapsulant 42 is either heat cured, UV cured or left to harden by methods well known in the art. FIG. 2E is an overhead plan view of a prior art multi-package array 200. As shown in FIG. 2E, once layer of encapsulant 42 hardens, a plurality of packaged electronic components 10 and 10A are created in a multi-package array 200 including prior art packaged electronic components 10 and 10A.
Fabricating a plurality of packaged electronic components 10 and 10A simultaneously (in contrast to individually) from a single prior art multi-package array substrate 13, by the prior art methods discussed above, advantageously reduces handling costs and thereby reduces the cost of fabricating each individual packaged electronic component 10 and 10A. However, the individual packaged electronic components 10 and 10A must still be separated or xe2x80x9csigulatedxe2x80x9d from multi-package array 200 before they can be put to use.
FIG. 3A, FIG. 3B, and FIG. 3C illustrate a typical prior art method for the singulation of individual packaged electronic components 10 and 10A from a multi-package array 200. FIG. 3A is an enlarged cross-sectional view of a prior art multi-package array 200 as would be seen looking along line IIIAxe2x80x94IIIA of FIG. 2E.
Referring to FIG. 3A, multi-package array 200 includes a prior art multi-package substrate 13 having a plurality of sections 12 and 12A. After singulation, a packaged electronic component 10 and 10A is formed from each section 12 and 12A, respectively. Referring to an exemplary section 12A of the plurality of sections 12, metallizations 22 and 26 are formed on first and second surfaces 18 and 20, respectively. Corresponding metallizations 22 and 26 are electrically connected to one another by conductive through-holes 14. Contacts 23 and 27 are formed on corresponding metallizations 22 and 26, respectively. A solder mask 39 is placed over portions of second surface 20 and metallizations 26 but does not cover contacts 27.
Electronic components such as integrated circuits 30 and 30A, sometimes called IC chips, are attached to first surface 18 of sections 12 and 12A, respectively by adhesive 34. Bond pads 38, sometimes called bonding pads, are electrically connected to corresponding a-contacts 23 by corresponding bond wires 40.
As discussed above, a hardened layer of encapsulant 42 covers integrated circuits 30 and 30A including bond pads 38, bond wires 40, contacts 23, metallizations 22 and the remaining exposed first surface 18 of substrate 13.
As shown in FIG. 3B, to begin the prior art singulation process, prior art multi-package array 200 is placed upside down on tape 332 such that layer of encapsulant 42 adheres to a tape 332 and fiducials 345 are extended upwards and are exposed.
Tape 332 supports array 200 during sawing and is necessitated by the fact that, using prior art methods, a saw blade 322 cuts completely through substrate 13 and layer of encapsulant 42 as discussed in more detail below. Tape 332 is typically a sticky film or tape known to those of skill in the art as xe2x80x9cblue tapexe2x80x9d. Disadvantageously, the use of tape 332 not only adds the cost of the tape itself to the process, but also the additional equipment required to apply and remove tape 332 and the time involved doing so.
Prior art multi-package array 200 is then singulated by cutting from backside surface 300B using fiducials 345 as a reference. FIG. 3B is a cross-sectional view of prior art multi-package array 200 of FIG. 2E and FIG. 3A being cut from backside surface 300B. Saw blade 322 is aligned with multi-package array 200. Typically, optical or mechanical alignment systems (not shown), which are well known to those of skill in the art, align saw blade 322 to array 200. Saw blade 322 has a thickness 370. Thickness 370 ranges from 3 to 14 mils and is typically on the order of 9 to 12 mils (note, a mil is defined as {fraction (1/1000)} of an inch herein). Saw blade 322 is then carefully aligned so that prior art multi-package array substrate 13 and layer of encapsulant 42 are cut along peripheries 56 of sections 12 and 12A (e.g., see lines 56, 58 of FIG. 1A discussed above) and packaged electronic components 10 and 10A, respectively, are singulated. As seen in FIG. 3B, an exemplary packaged electronic component 10A includes section 12A and the attached integrated circuit 30A.
After singulation, packaged electronic components 10 must be washed, typically with de-ionized water or solvent, to remove particulates of debris 366 (FIG. 3B). Disadvantageously, the washing process often leaves solder balls 28 (FIG. 3A) tarnished which can interfere with the conductivity of solder balls 28. In addition, de-ionized water is costly and solvents can be an environmental hazard requiring special permits and disposal mechanisms.
Next, packaged electronic components 10 are removed from tape 332 and inverted by a pick and place machine (not shown). Pick and place machines are well known in the art and come in several models from various makers and/or distributors.
A pick and place machine (not shown) then attaches to layer of encapsulant 42 of packaged electronic component 10A and removes packaged electronic components 10A for shipment wrapping or further processing by methods well known to those of skill in the art. The other packaged electronic components 10 are then similarly removed and processed.
The prior art sigulation process discussed above is extremely complicated, labor intensive and difficult to perform correctly. The process also involves highly specialized equipment such as optical alignment equipment, specialized saws, saw controls, pick and place machines, blue tape, and de-ionized water or solvents. This specialized equipment is expensive, bulky, typically not mobile, and requires skilled operators. Consequently, using prior art methods and structures, the singulation process must be performed at the packaging factory. This in turn means that each packaged electronic component must be shipped separately and wrapped separately, thus driving up the cost of each packaged electronic component, increasing the probability of defective units by increasing handling operations and driving down the efficiency of the process.
In contrast, systems manufacturers, the typical customers for packaged electronic components, desire packages that adequately protect the electronic components and allow these components to be shipped in bulk, cheaply and safely, to remote assembly locations. The systems manufactures further desire packaged electronic components that can be stored, efficiently and economically, for long periods of time and can then be assembled directly into the systems, at the assembly site, without significant further processing of the packaged electronic components. As discussed above, prior art methods, especially prior art singulation methods, do not meet this need.
In addition to failing to meet the needs of the customer, prior art singulation methods also waste expensive resources, including substrate material, blue tape, de-ionized water, solvents and time. As discussed above, saw blade 322 has thickness 370 and saw blade 322, like any saw, cuts unevenly leaving a trough or kerf 375 with relatively rough edges 375A and 375B (FIG. 3C). Consequently, kerf 375 has an associated kerf thickness 372 that is typically even greater than saw thickness 370 and is often on the order of 3 to 14 mils.
FIG. 3C is an enlarged view of section 380 of FIG. 3B showing kerf 375, of kerf thickness 372, including kerf sides 375A, 375B, and kerf bottom 375C. Each cut in multi-package array 200 results in a kerf 375, with an associated kerf thickness 372 that runs completely through prior art multi-package substrate 13 and layer of encapsulant 42. Therefore, using prior art methods, blue tape 122 is required to hold prior art multi-package array substrate 13 together during the singulation process. In addition, space must be left between packaged electronic components 10 on multi-package array 200 to allow for cutting and the resulting kerf 379. Disadvantageously, this area allocated for the cutting process means that fewer packaged electronic components 10 and 10A can be formed on each multi-package array 200 and the cost of each packaged electronic component 10 and 10A is increased.
The prior art methods discussed above also result in the loss of expensive substrate and encapsulant material. The material is lost when kerfs 375 are cut by saw blade 322. The material lost with each cut is equal to kerf thickness 372 times the length (not shown) of kerf 375. In a typical prior art embodiment, kerf 375 is on the order of 2 inches to 78.5 millimeters long. Since each packaged electronic component 10 and 10A is typically cut on all four sides, the amount of material lost is considerable. This fact also adds significantly to the cost of each individual packaged electronic component 10 and 10A.
As shown in FIG. 3B, saw blade 322, and the sawing process in general, creates particulates of debris 366 during the singulation process. Particulates of debris 366 are disadvantageous since they can contaminate packaged electronic components 10 and 10A. In addition, during the sawing process, the integrity of packaged electronic components 10 and 10A is often compromised due to the stress created by the sawing process and/or improper alignment of saw blade 322. Consequently, it often happens that the sawing process first compromises the integrity of packaged electronic components 10 and 10A and then provides the contamination in the form of particulates of debris 366. This is clearly a disadvantage of the prior art methods.
Another prior art method for sigulation (not shown), uses a LASER to cut along lines 56 and 58 and thereby singulate packaged electronic components 10 and 10A. Using the LASER method, far fewer particulates of debris 366 are created. However, space must still be allocated for the cutting process which means that fewer packaged electronic components 10 and 10A can be formed on each multi-package array 200 and the cost of each packaged electronic component 10 and 10A in increased. In addition, the cost of the specialized LASER equipment, along with the trained operators to run the equipment, is significant and often economically prohibitive. The LASER equipment is also typically not portable. This means the singulation process must still be performed at the packaging location. Using the prior art LASER singulation method also requires very careful alignment and package integrity is often compromised by a misaligned LASER. This situation also dictates that singulation be performed at the packaging plant rather than in the field.
The labor, preparation and machinery involved in the prior art singulation process, as well as the waste and other problems associated with the prior art process, make singulation using prior art methods one of the most expensive and wasteful steps in the packaging process. What is needed is a method and structure for packaging electronic components that allows for singulation of individually packaged electronic components from a multi-package array that is simple, economical, does not require specialized singulation equipment and allows for singuation onsite or in the field.
In accordance with the present invention, a snapable multi-package substrate is formed with trenches that separate and define sections where individual packaged electronic components are fabricated in a snapable multi-package array. Individual packaged electronic components are sigulated from the snapable multi-package array of the invention by simply applying hand pressure to break or xe2x80x9csnapxe2x80x9d individual packaged electronic components apart.
The singulation process using the method and structure of the invention does not require any specialized equipment such as optical alignment devices, specialized saws and saw controls or pick and place machines. The singulation process using the method and structure of the invention does not require skilled operators. Consequently, singulation, using the method and structure of the invention, can be performed anywhere and packaged electronic components can be shipped in snapable multi-package arrays, stored in snapable multi-package arrays for long periods of time, and then be singulated and assembled directly into the systems, at the assembly site, without significant further processing of the snapable packaged electronic components.
In addition, the waste associated with prior art singulation methods is eliminated. With no saw or saw blade, and no cuts or kerfs completely through the substrate and layer of encapsulant, there is no concern about saw blade thickness and kerf or kerf thickness. Consequently, no space must be left between packaged electronic components on snapable multi-package array to allow room for cutting and the resulting kerfs. This means more packaged electronic components can be formed on each snapable multi-package array and the cost of each packaged electronic component is decreased.
In addition, using the method and structure of the invention for singulation, no blue tape is required and no material is lost because there are no kerfs cut completely through the substrate and encapsulant by a saw blade. Since each packaged electronic component is typically cut on all four sides using prior art methods, the amount of material saved using the structure and method of the invention is considerable.
In addition, since the singulation process using the method and structure of the invention does not involve a saw, there are no alignment problems or stresses associated with sawing and no particulates of debris are created. Consequently, using the method and structure of the invention, there is less chance to contaminate the packaged electronic components and no washing is required or de-ionized water or solvents.
These and other features and advantages of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.